发明名称 |
Maintaining Circuit Delay Characteristics During Power Management Mode |
摘要 |
A system and method for maintaining circuit delay characteristics during power management mode. The method for maintaining circuit delay characteristics during power management mode continually toggles the clock distribution circuits at a frequency sufficiently low that it does not significantly impact chip power dissipation. The clock frequency used to toggle the clock distribution circuits is high enough to minimize the asymmetrical stress on the clock buffer transistors so that both P and N device characteristics equally change over time.
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申请公布号 |
US2009121747(A1) |
申请公布日期 |
2009.05.14 |
申请号 |
US20070938347 |
申请日期 |
2007.11.12 |
申请人 |
DHONG SANG HOO;HOFSTEE PETER HARM;RILEY MACK WAYNE;WARNOCK JAMES DOUGLAS;WEITZEL STEPHEN DOUGLAS |
发明人 |
DHONG SANG HOO;HOFSTEE PETER HARM;RILEY MACK WAYNE;WARNOCK JAMES DOUGLAS;WEITZEL STEPHEN DOUGLAS |
分类号 |
H03K3/017 |
主分类号 |
H03K3/017 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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