发明名称 MULTIPLIER CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a multiplier circuit which has a small variation in production because no resistance is used, allows simple temperature correction of output voltage and is preferable to be formed on a semiconductor integrated circuit. SOLUTION: The multiplier circuit has first and second square circuits configured such that differential MOS transistors (M1 and M2) and (M4 and M5) are vertically stacked (cascode-connected) on diode-connected MOS transistors (M3 and M6). The first and second square circuits receive respective inputs which are a differential addition voltage (Vx+Vy) and a differential subtraction voltage (Vx-Vy) of a first input voltage (Vx) and a second input voltage (Vy). Outputs of the first and second square circuits are first and second terminal voltages of the diode-connected MOS transistors (M3 and M6), respectively. A differential voltage of the first and second terminal voltages corresponds to the product of the first input voltage and the second input voltage. COPYRIGHT: (C)2009,JPO&INPIT
申请公布号 JP2009104463(A) 申请公布日期 2009.05.14
申请号 JP20070276611 申请日期 2007.10.24
申请人 NEC ELECTRONICS CORP 发明人 KIMURA KATSUHARU
分类号 G06G7/16 主分类号 G06G7/16
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