发明名称 |
Semiconductor device having a metal gate electrode formed on an annealed high-k gate dielectric layer |
摘要 |
A method of forming a transistor gate stack having an annealed gate dielectric layer begins by providing a substrate that includes a first and second spacer separated by a trench. A conformal high-k gate dielectric layer is deposited on the substrate and within the trench with a thickness that ranges from 3 Å to 60 Å. Next, a capping layer is deposited on the high-k gate dielectric layer that substantially fills the trench and covers the high-k gate dielectric layer. The high-k gate dielectric layer is then annealed at a temperature that is greater than or equal to 600° C. The capping layer is removed to expose an annealed high-k gate dielectric layer. A metal layer is then deposited on the annealed high-k gate dielectric layer. A CMP process may be used to remove excess material and complete formation of the transistor gate stack.
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申请公布号 |
US7531404(B2) |
申请公布日期 |
2009.05.12 |
申请号 |
US20050216596 |
申请日期 |
2005.08.30 |
申请人 |
INTEL CORPORATION |
发明人 |
PAE SANGWOO;MAIZ JOSE;BRASK JUSTIN;DEWEY GILBERT;KAVALIEROS JACK;CHAU ROBERT;DATTA SUMAN |
分类号 |
H01L21/8238;H01L21/3205;H01L21/336;H01L21/8234 |
主分类号 |
H01L21/8238 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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