| 摘要 |
A test pattern generator generating a test pattern for performance testing of an onboard memory is provided for a device having a memory macro, a serial input interface, and a latch circuit latching the serial input signal and outputting the result to the memory macro in parallel format. This test pattern generator has an address generator generating multi-bit addresses, parallel-serial converters parallel-serial converting the multi-bit addresses generated by the address generator into a plurality of address groups, and a controller performing control to output the converted address groups serially to the device in a plurality of cycles, comparing addresses already output to the device and addresses to be output to the device, and performing control to output only address groups having cycles corresponding to differing bits through comparing to the device.
|
