发明名称 Network-on-chip dataflow architecture
摘要 Network-on-Chip Dataflow Architecture is the new microprocessor architecture. It consists of many processing elements connecting together via two distinct networks namely instruction network and data network. Instructions are fetched into the processing elements through instruction network which uses packet switching scheme. Then the instructions will configure the processing elements and connections of the data network to create a dataflow graph. After that data are transferred and processed by the graph in a dataflow manner. Our architecture has one special characteristic in which instructions within loops are fetched only once but they are used many times.
申请公布号 US7533244(B2) 申请公布日期 2009.05.12
申请号 US20060382382 申请日期 2006.05.09
申请人 TRAN LE NGUYEN 发明人 TRAN LE NGUYEN
分类号 G06F15/82 主分类号 G06F15/82
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