| 摘要 |
A demodulator circuit for demodulating a signal modulated by frequency shift keying discriminates the frequency of the signal to produce demodulated data. When the demodulated data match a known synchronization pattern, or are complementary to the known synchronization pattern, the demodulator circuit latches a value indicating whether the demodulated data match or are complementary to the synchronization pattern. If the latched signal indicates matching data, subsequent demodulated data are output as is. If the latched signal indicates complementary data, subsequent demodulated data are inverted and the inverted data are output. The output data are therefore correct even if the demodulated data are inverted.
|
