发明名称 Processor secured against traps
摘要 A method for controlling the execution of a program including of associating with each operator an initial digital code and a final digital code which are linked to each other by a degradation function applied a number of times depending on the execution of this operator; applying, to the content of a register initialized at each instruction beginning by the initial code of the corresponding operator, said degradation function a number of times depending on the operator execution; and checking, at least at each instruction end, the coherence between the register content and the final code of the corresponding operator.
申请公布号 US7533412(B2) 申请公布日期 2009.05.12
申请号 US20030418523 申请日期 2003.04.18
申请人 STMICROELECTRONICS S.A. 发明人 TEGLIA YANNICK
分类号 G06F12/14;G06F1/00;G06F21/00;G06F21/52;H04L9/00 主分类号 G06F12/14
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