发明名称 SIGNALING WITH SUPERIMPOSED CLOCK AND DATA SIGNALS
摘要 <p>A data transmission circuit includes a clock driver to obtain a clock signal having a first rate and to drive the clock signal onto one or more transmission lines. The data transmission circuit also includes a timing circuit to obtain the clock signal and to generate a symbol clock having a second rate. The first rate is a multiple of the second rate, wherein the multiple is greater than one. The data transmission circuit further includes a data driver synchronized to the symbol clock. The data driver obtains a data signal and drives the data signal onto the one or more transmission lines at the second rate. The data signal and the clock signal are driven onto the one or more transmission lines simultaneously.</p>
申请公布号 WO2009058789(A1) 申请公布日期 2009.05.07
申请号 WO2008US81477 申请日期 2008.10.28
申请人 RAMBUS INC.;LIN, QI;KIM, JAEHA;LEIBOWITZ, BRIAN, S.;ZERBE, JARED, L.;REN, JIHONG 发明人 LIN, QI;KIM, JAEHA;LEIBOWITZ, BRIAN, S.;ZERBE, JARED, L.;REN, JIHONG
分类号 H04L7/027;H04L7/00 主分类号 H04L7/027
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