发明名称 METHOD AND SYSTEM FOR ELIMINATING DC BIAS ON ELECTROLYTIC CAPACITORS AND SHUTDOWN DETECTING CIRCUIT FOR CURRENT FED BALLAST
摘要 A system and method is provided that eliminates DC bias on at least one of a first electrolytic capacitor and a second electrolytic capacitor of a bipolar junction transistor (BJT) based inverter ballast having a shutdown control circuit in association with only one of at least two BJT switches. A duty cycle dependent capacitor is connected in a series with a bus of the ballast, and a resonant circuit, including primary winding of the output transformer and a resonant capacitor. A balancing/charging resistor is connected at one end between the first electrolytic capacitor and the second electrolytic capacitor, and at another end to the duty cycle dependent capacitor and the resonant circuit.
申请公布号 US2009115340(A1) 申请公布日期 2009.05.07
申请号 US20070934943 申请日期 2007.11.05
申请人 GENERAL ELECTRIC COMPANY 发明人 CHEN TIMOTHY;MIAO HAILIANG;KUMAR NITIN
分类号 H05B41/24 主分类号 H05B41/24
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