| 摘要 |
A semiconductor memory device can a desired internal clock in consideration of a delay time of an actual clock/data path. The semiconductor memory device includes a multiclock signal generating unit configured to receive a reference clock signal and generate a plurality of clock signals having a constant phase difference from each other, a delay modeling unit configured to generate a plurality of delay clock signals by reflecting a delay time of an actual clock/data path to the plurality of clock signals, a selection signal generating unit configured to generate selection signals by comparing phases between the reference clock signal and the plurality of delay clock signals, and a phase multiplexing unit configured to output any one of the plurality of clock signals as a final clock signal in response to the selection signals.
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