| 摘要 |
An arithmetic processing apparatus includes a cache block which stores a plurality of instruction codes from a main memory, a central processing unit which fetch-accesses the cache block and sequentially loads and executes the plurality of instruction codes, and a repeat buffer which stores an instruction code group corresponding to a buffer size, the instruction code group ranging from a head instruction code to a terminal instruction code among the head instruction code to an end instruction code of a repeat block repeatedly executed in the processing program, in the plurality of instruction codes stored in the cache block. The arithmetic processing apparatus further includes an instruction cache control unit which performs control so that the instruction code group stored in the repeat buffer is selected and supplied to the central processing unit when the repeat block is repeatedly executed.
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