发明名称 Floating Body Memory Cell System and Method of Manufacture
摘要 A plurality of integrated circuit features are provided in the context of an array of memory cells including a plurality of word lines and a plurality of bit lines. Each memory cell includes a floating body or is volatile memory. The aforementioned features may include, among others, an option whereby the foregoing bit lines may be situated below a channel region of corresponding memory cells, etc.
申请公布号 US2009116270(A1) 申请公布日期 2009.05.07
申请号 US20070923713 申请日期 2007.10.25
申请人 MATRIX SEMICONDUCTOR, INC. 发明人 SCHEUERLEIN ROY E.
分类号 G11C5/02;G11C5/06;G11C8/10;H01L21/00;H01L29/66 主分类号 G11C5/02
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