发明名称 |
Digital delay locked loop circuit using mode register set |
摘要 |
A semiconductor memory device includes a mode register set for establishing information on a delay time, a delay time calculator for calculating an I/O path delay time of a data clock on a basis of a unit period of a system clock, and a delay locked clock generator for reflecting in the data clock a value of subtracting an output of the delay time calculator from the information established in the mode register set.
|
申请公布号 |
US2009119533(A1) |
申请公布日期 |
2009.05.07 |
申请号 |
US20070005917 |
申请日期 |
2007.12.28 |
申请人 |
HYNIX SEMICONDUCTOR INC. |
发明人 |
KIM BO-KYEOM;YOON SANG-SIK |
分类号 |
G06F1/12;G06F1/08;G06F11/07 |
主分类号 |
G06F1/12 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|