发明名称 METHOD AND SYSTEM FOR CLOCK CONTROL FOR POWER-STATE TRANSISTIONS
摘要 <p>Clock management is implemented using a variety of systems, devices and methods. According to one embodiment a clock transitioning circuit arrangement (104) is implemented for receiving data from a processor system (102) via a data bus (212, 214) and for modifying a state a clock-generation unit (106) having a local memory for controlling a plurality of clock outputs that provide clock signals for use by the processing system (102). The arrangement has a memory circuit (206) for storing the data from the processor system (102) and a control circuit (208) for accessing the data in the memory circuit (206) in response to a request to change a clock signal provided by an output of the plurality of clock outputs and for providing corresponding data to the local memory of the clock generation unit (106).</p>
申请公布号 WO2009057008(A1) 申请公布日期 2009.05.07
申请号 WO2008IB54263 申请日期 2008.10.16
申请人 NXP B.V.;EHMANN, GREG 发明人 EHMANN, GREG
分类号 G06F13/42;G06F1/04;G06F1/32 主分类号 G06F13/42
代理机构 代理人
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