发明名称 Solving Via-Misalignment Issues in Interconnect Structures Having Air-Gaps
摘要 An integrated circuit structure is provided. The integrated circuit structure includes a semiconductor substrate; and a metallization layer over the semiconductor substrate. The metallization layer includes a conductive line; a low-k dielectric region adjacent and horizontally spaced apart from the conductive line by a space; and a filler dielectric material filling at least a portion of the space, wherein the filler dielectric material and the low-k dielectric region are formed of different materials. The integrated circuit structure further includes a capping layer over and adjoining the filler dielectric material and the low-k dielectric region. The filler dielectric material has a dielectric constant (k value) less than a k value of the capping layer.
申请公布号 US2009115061(A1) 申请公布日期 2009.05.07
申请号 US20070933929 申请日期 2007.11.01
申请人 CHEN HSIEN-WEI 发明人 CHEN HSIEN-WEI
分类号 H01L23/52 主分类号 H01L23/52
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