发明名称 DEFECT ANALYZER AND DEFECT ANALYZING METHOD
摘要 PROBLEM TO BE SOLVED: To provide a defect analyzer and defect analyzing method for performing highly precise defect analysis. SOLUTION: A defect analyzer has a region dividing section 12 configured to divide a defect analyzing region of a wafer into a plurality of grid squares, the wafer having a circuit pattern formed thereon, a pattern feature quantity extracting section 13 configured to extract a pattern feature quantity based on design data of the circuit pattern for each of the grid squares, a region classifying section 14 configured to classify the plurality of grid squares into a plurality of groups based on the pattern feature quantities, a defect coordinate matching section 15 configured to match defect information having been detected in the defect analyzing region with the defect analyzing region, a defect size distribution calculating section 16 configured to calculate a defect size distribution in each of the plurality of groups, a distribution comparing section 17 configured to compare the defect size distribution and a predetermined estimation distribution in each of the plurality of groups and calculate a difference, and a region extracting section 18 configured to output the defect information corresponding to the group having the difference equal to or smaller than the threshold value. COPYRIGHT: (C)2009,JPO&INPIT
申请公布号 JP2009098123(A) 申请公布日期 2009.05.07
申请号 JP20080149303 申请日期 2008.06.06
申请人 TOSHIBA CORP 发明人 SATO YOSHIYUKI
分类号 G01B11/30;G01N21/956;H01L21/66 主分类号 G01B11/30
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