发明名称 Clock control circuit and data alignment circuit including the same
摘要 A clock control circuit can prevent a malfunction that occurs when a rising strobe signal and a falling strobe signal change in pulse width and thus overlap each other. The clock control circuit which includes a first clock control unit configured to receive a rising strobe signal and a falling strobe signal and output an adjusted rising strobe signal, an enable pulse width of which does not overlap an enable pulse width of the falling strobe signal.
申请公布号 US2009115480(A1) 申请公布日期 2009.05.07
申请号 US20070006113 申请日期 2007.12.31
申请人 HYNIX SEMICONDUCTOR INC. 发明人 JANG JI-EUN;YOON SEOK-CHEOL
分类号 H03K3/017 主分类号 H03K3/017
代理机构 代理人
主权项
地址