| 摘要 |
A programmable delay lock loop system provides a delayed output signal (106, fig. 1) having a programmed delay relative to an input signal (102, fig.1). A phase detector (108, fig.1) provides a phase delay signal indicative of an actual phase difference between the input signal and the delayed output signal. An accumulator (116, fig.1) provides a delay control signal 118 as a function of a difference between a commanded delay (112, fig.1) and the actual phase difference. A programmable phase delay circuit (fig.3) includes an input frequency doubler 302. The circuit is configured to generate a ramp signal 303 based upon the output of the input frequency doubler, and to adjust the DC bias of the ramp signal in response to the delay control signal 118. The ramp signal 303 is compared with a threshold level (502, fig.5) in comparator 314. The output of the comparator is pulse signal 315 whose pulse width depends on the bias of the ramp signal 303 (figs. 5 and 6). The output of the comparator is used to clock a latch 316 which produces the delayed output signal 106 (figs.3, 5 and 6). The circuit may find use in an optical phase domain reflectometer (OPDR) in unmanned aerial vehicles (UAVs) or other aerospace settings. |
