| 摘要 |
<p>A data processor maps input data symbols to be communicated onto a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol. The data processor includes an interleaver memory which reads-in the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals. The interleaver memory reads-out the data symbols on to the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on to the sub-carrier signals. The set of addresses are generated from an address generator which comprises a linear feedback shift register and a permutation circuit. A generator polynomial for the linear feedback shift register is R i ¹ 8 = R i - 1 ¹ 0 Š• R i - 1 ¹ 4 , and a permutation code is provided for permuting the order of the content of the register stages. The permutation code has been established by simulation analysis to optimise communication performance via typical radio channels. As such, a 1K operating is provided with an interleaver, which can interleave data symbols onto approximately one thousand sub-carriers of OFDM symbols for an OFDM modulated system such as a Digital Video Broadcasting (DVB) standard such as DVB-Terrestria12 (DVB-T2) or DVB-Cable2.</p> |
