Combined Magnitude Detection and Arithmetic Operation

摘要

The invention comprises an apparatus that consists of processing circuitry, one or more registers and control circuitry. The control circuitry is configured to be responsive to a combined magnitude-detecting arithmetic instruction to control the processing circuitry to perform an arithmetic operation on at least one data element in the one or more registers and further to perform a magnitude-detecting operation on the values. The magnitude-detecting operation calculates an indication of the position of the most-significant bit of a magnitude of the arithmetic operation irrespective of whether the most-significant bit position exceeds the data element width of the at least one data element.