| 摘要 |
Generally described, embodiments of the present invention are directed at reducing the power consumed by a CPU. In accordance with one embodiment, a method is provided that transitions the CPU into a reduced power state in response to a fetch operation being dispatched to an I/O device. More specifically, the method includes comparing the latency associated with recovering from a reduced power state with the time remaining before a timer expires. Then, a signal is generated that identifies a timer-specific reduced power state. The method aggregates signals received from different timers to identify a reduced power that is appropriate given all of the processing that is scheduled to be performed.
|
