Apparatus and method for instruction-level specification of floating point format

摘要

Apparatus and method are provided for extending a microprocessor instruction set to allow for instruction-level specification of floating point format to be employed during execution of an associated floating point operation. The apparatus includes translation logic and extended execution logic. The translation logic translates an extended instruction into corresponding micro instructions. The extended instruction has an extended prefix and an extended prefix tag. The extended prefix specifies the floating point format. The extended prefix tag indicates the extended prefix, where the extended prefix tag is an otherwise architecturally specified opcode within an instruction set for a microprocessor. The extended execution logic is coupled to the translation logic. The extended execution logic receives the corresponding micro instructions, and executes the associated floating point operation according to the floating point format specified by the extended prefix.