Series and parallel operation of reconfigurable circuits with selection and timing buffers assembly for processing and binding divided data portions in matched timing

摘要

A reconfigurable processor equipped with reconfigurable circuits (RCs) comprises unit A for dividing data input to the processor, and outputting a part of pieces of divided data to a RC, unit B for selecting or binding at least one piece of divided data among divided data which is not outputted from the input data dividing unit and output data of the RC to output processed data to other RCs, at least one RS buffer for temporarily storing data input to unit B to match timings of output from the RC and output from the RS buffer, unit C for binding the output data of the RC, unit A, and unit B to output data from the processor, and at least one RO buffer for temporarily storing data input to unit C to match the timings of output from the RC, output from unit A, and output from unit B.