| 摘要 |
PROBLEM TO BE SOLVED: To provide data inversion register technique for integrated circuit memory testing in which data input signals are selectively inverted in a predetermined patten to maximize the probability of identifying failures during testing. SOLUTION: On predetermined input/outputs (I/O), data inputs may be inverted to create a desired test pattern (such as stripes) which are "worst case" for I/O circuitry or column stripes which are "worst case" for memory arrays. Next, the technique of the present invention matches the pattern for the data output path, inverting the appropriate data outputs to obtain the expected tester data. In this way, the test mode is transparent to any memory tester. COPYRIGHT: (C)2009,JPO&INPIT
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