| 摘要 |
PROBLEM TO BE SOLVED: To verify a logic circuit under test by simulation at high speed. SOLUTION: A BIST circuit 3 which tests the logic circuit 4 under test comprises a control circuit 11, a test pattern generation circuit 12, a first pattern generation circuit 13, a second pattern generation circuit 14, a signal compression pattern generation circuit 15 and a failure detection analysis circuit 16. A test pattern to the logic circuit 4 generated in the test pattern generation circuit 12 is forcedly assigned to a corresponding scan flip-flop as a PLS input test pattern by the first test pattern generation circuit 13. The assigned test pattern is subjected to simulation with delay in an interlocking simulator part 5. The result of simulation with delay fetched by the second test pattern generation circuit 15 is forcedly assigned to the corresponding scan flip-flop as a PLS test pattern with expected value. COPYRIGHT: (C)2009,JPO&INPIT
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