| 摘要 |
A circuit for generating a data output enable signal is provided to prevent data output timing error by generating output enable signal. A delay locked loop circuit(40) outputs to the rising delay / fixed loop clock(RCLKDLL) and polling delay / fixed loop clock(FCLKDLL) by fixing the external clock(CLK) a delay. A data output enable signal generation circuit(42) generates a reference output enable signal having the width of a pulse corresponding to a bust length. An output driver is synchronized to data output enable signal and outputs the output data by driving the data. |
