发明名称 SEMICONDUCTOR MEMORY DEVICE
摘要 PROBLEM TO BE SOLVED: To perform circuit examination for error correction without any influence of a memory cell. SOLUTION: The semiconductor memory device includes a parity generating circuit for generating parity data corresponding to input data, a normal data latching section for latching input data or data read from a normal memory cell array, an input selection circuit for selectively outputting the input data or the parity data, a parity data latching section for latching and outputting an output from the input selection circuit or data read from the parity memory cell array, and an error correction circuit for performing error detection on the data latched by the normal data latching section by using the data latched by the parity data latching section, and performing error correction if an error is detected, to output the obtained result. The parity data latching section outputs the data latched by itself externally of the semiconductor memory device. COPYRIGHT: (C)2009,JPO&INPIT
申请公布号 JP2009093714(A) 申请公布日期 2009.04.30
申请号 JP20070261222 申请日期 2007.10.04
申请人 PANASONIC CORP 发明人 SADAKATA HIROYUKI;IIDA MASAHISA
分类号 G11C29/42 主分类号 G11C29/42
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