| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To shorten the function verification time of an asynchronous circuit by reducing the number of times of the function verification of the asynchronous circuit in a meta stable state. <P>SOLUTION: The circuit verifying apparatus 10 comprises an input data detection part 252 which detects a change of input data Di in synchronization with a first clock signal CLK1 input to a transmitting-side sequential circuit FF1; a logic circuit arithmetic part 251 which performs processing to make a receiving-side sequential circuit FF2 output information Dm showing a meta stable state during a period longer than one period of the first clock signal CLK1 based on the change of the input data Di; and a storage device 13 which stores the changed input data based on the change of the input data Di. <P>COPYRIGHT: (C)2009,JPO&INPIT</p> |
