发明名称 |
Method for Improved Power Distribution in a Three Dimensional Vertical Integrated Circuit |
摘要 |
A first through via is electrically insulated from surrounding wafer substrate material. A second through via is not electrically insulated from the surrounding wafer substrate material. This configuration is advantageous when the non-insulated via serves as the path for either Vdd or GND. By not insulating the through via, a first supply voltage (Vdd or GND) is allowed to flow through the surrounding wafer substrate material thereby decreasing the resistance of the first supply voltage path. |
申请公布号 |
US2009111214(A1) |
申请公布日期 |
2009.04.30 |
申请号 |
US20070928181 |
申请日期 |
2007.10.30 |
申请人 |
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发明人 |
CHRISTENSEN TODD ALAN;SHEETS, II JOHN EDWARD |
分类号 |
H01L21/60 |
主分类号 |
H01L21/60 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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