| 摘要 |
An array of nonvolatile memory cells comprises a substantially single crystalline semiconductor substrate of a first conductivity type, having a planar surface. A plurality of non-volatile memory cell units are arranged in a plurality of rows and columns in the substrate. Each cell unit comprises a first region of a second conductivity type in the substrate along the planar surface. A second region of the second conductivity type is in the substrate along the planar surface, spaced apart from the first region. A channel region is between the first region and the second region. The channel region is characterized by three portions: a first portion, a second portion and a third portion, with the second portion between the first portion and the third portion, and the first portion adjacent to the first region, and the third portion adjacent to the second region. A first floating gate is over the first portion of the channel region, and is insulated therefrom. A first control gate is over the first floating gate and is capacitively coupled thereto. A first erase gate is over the first region and is insulated therefrom. A word line is over the second portion and is insulated therefrom. A second erase gate is over the second region and is insulated therefrom. A second floating gate is over the third portion and is insulated therefrom. A second control gate is over the second floating gate and is capacitively coupled thereto. Cell units in the same row share the word line in common. Cell units in the same column share the first region in common to one side, the first erase gate in common, the second region in common to the other side and the second erase gate in common, and the first and second control gates in common. Cell units in the same column share the first control gate in common and the second control gate in common. Electrical contacts are made to the array only along extremities of the array at first and second regions.
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