发明名称 SIGNAL CONVERTER FOR DEBUGGING THAT EXPANDS FIFO CAPACITY
摘要 A signal converter includes an interconnect interface, a FIFO set, which comprises a transmitter FIFO and a receiver FIFO respectively connected to the interconnect interface through a data bus, a parallel/serial converter connected to the transmitter FIFO and the receiver FIFO by two data buses respectively and kept apart from the FIFO set, and a serial I/O interface connected to the parallel/serial converter.
申请公布号 US2009113092(A1) 申请公布日期 2009.04.30
申请号 US20080247593 申请日期 2008.10.08
申请人 UNIVERSAL SCIENTIFIC INDUSTRIAL CO.,LTD. 发明人 HUNG WEN-LIANG;LIAO JYUN-DA
分类号 G06F13/42 主分类号 G06F13/42
代理机构 代理人
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