发明名称 MEMORY ACCESS CONTROL DEVICE AND MEMORY ACCESS CONTROL METHOD
摘要 PROBLEM TO BE SOLVED: To improve the using efficiency of a memory bus related with a memory access control technology. SOLUTION: A memory access control device for controlling access to a plurality of memory devices with differing latency stores a preissued preceding command and the information of the memory device to which the preceding command has been issued as preceding command information, and sets a command issue interval until the next command is issued on the basis of the next command to be issued the next and the information of the memory device which issues the next command and the preceding command information, and controls the issue of the next command according to the set command issue interval. COPYRIGHT: (C)2009,JPO&INPIT
申请公布号 JP2009093227(A) 申请公布日期 2009.04.30
申请号 JP20070260357 申请日期 2007.10.03
申请人 CANON INC 发明人 OCHIAI WATARU
分类号 G06F12/06;G06F12/00 主分类号 G06F12/06
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