发明名称 CONVERSION DEVICE, CONVERSION METHOD, PROGRAM, AND RECORDING MEDIUM
摘要 Provided are a conversion device and the like for converting a initial test pattern given in advance into a test pattern of a bit constitution of different logic values, without losing the fault coverage of transition delay fault which can be detected by the constitution element of the initial test pattern. The conversion device converts an initial test pattern 100a given in advance for a logic circuit into an intermediate test pattern 100b of a bit constitution of different logic values, where the constitution elements of the initial test pattern 100a are at least two test vectors applied in succession. The conversion device includes a decision means for deciding a combination of logic values in the initial test pattern 100a which meet a detection condition of faults of the logic circuit which can be detected by applying the constitution elements.
申请公布号 US2009113261(A1) 申请公布日期 2009.04.30
申请号 US20080345310 申请日期 2008.12.29
申请人 JAPAN SCIENCE AND TECHNOLOGY AGENCY;KYUSHU INSTITUTE OF TECHNOLOGY;SYSTEM JD CO., LTD. 发明人 KAJIHARA SEIJI;MIYASE KOHEI;WEN XIAQING;MINAMOTO YOSHIHIRO;DATE HIROSHI
分类号 G01R31/3177;G06F11/25 主分类号 G01R31/3177
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