发明名称 |
Limited Switch Dynamic Logic Cell Based Register |
摘要 |
A circuit that has a limited switch dynamic logic gate having a front end logic circuit and a latch. The output of the front end logic circuit is connected to an input of the latch, and the front end logic circuit evaluates a set of input signals applied to the front end logic circuit to generate an output signal. The latch receives and holds the output signal. The circuit also has a logic circuit having an output connected to a clock input in the front end logic circuit. The logic circuit generates a modified clock signal in response to receiving a clock signal from a clock source, and the modified clock signal has a duration that provides a minimum period of time for the front end logic to evaluate the set of input signals and generate the output signal.
|
申请公布号 |
US2009108874(A1) |
申请公布日期 |
2009.04.30 |
申请号 |
US20080172656 |
申请日期 |
2008.07.14 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
KLIM PETER J.;LAW JETHRO C.;LUONG TRONG V.;MATHEWS ABRAHAM |
分类号 |
H03K19/096;H03K19/00 |
主分类号 |
H03K19/096 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|