发明名称 METHOD OF ANALYZING CIRCUIT MODEL BY REDUCTION
摘要 A method for reducing and interpreting a circuit model is provided to efficiently perform the reduction-interpretation for the circuit model including an RC tree network consisting of large linear unmovable resistance and grounded capacitance and many independent current sources. Net list and node state information, namely the information about the original circuit configuration including independent current sources and node states, is inputted(301). The circuit net list comprising the independent current sources is pre-processed. A node to be removed is selected(302) and then is removed. A reduction circuit is generated(303). It is determined whether the additional reduction is needed(304). The reduction circuit is outputted(305).
申请公布号 KR20090042768(A) 申请公布日期 2009.04.30
申请号 KR20090024564 申请日期 2009.03.23
申请人 POSTECH ACADEMY-INDUSTRY FOUNDATION 发明人 CHE HONG BO;KIM, YOUNG HWAN
分类号 G06F17/50;G06F9/00 主分类号 G06F17/50
代理机构 代理人
主权项
地址