| 摘要 |
PROBLEM TO BE SOLVED: To provide a test pattern evaluation method and an evaluation device capable of performing evaluation in a reliability test accurately and properly, while reducing a simulation time, by a simulator having a gate level having comparatively short simulation time, or higher. SOLUTION: It is assumed that each possible internal state of a cell determined at least by a logic value or a voltage value of an input terminal is a cell state, and each possible state of a transistor determined by a voltage between terminals is a transistor state. The method includes: a cell state acquisition process for verifying operation of a semiconductor integrated circuit at a gate level or higher, and acquiring an appearance cell state continuously appearing for a predetermined time or more in the operation verification; a transistor state acquisition process for acquiring an appearance transistor state using the corresponding appearance cell state in the operation verification for each transistor; and a test activity calculation process for calculating a test activity ratio of the transistor using the corresponding appearance transistor state for each transistor. COPYRIGHT: (C)2009,JPO&INPIT
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