APPARATUS AND METHOD FOR OPTIMIZING DELAY ELEMENT IN ASYNCHRONOUS DIGITAL CIRCUITS

摘要

A computer readable storage medium includes executable instructions to construct a delay element to replicate the timing of critical gates and paths within a segment of an asynchronous circuit. The rise and fall delay mismatch of the delay element is minimized without obeying timing constraints. The position of each output of the delay element is determined to include a globally shared node within the segment and a non-shared local node in the segment.