发明名称 |
Integrated circuit stacking system and method |
摘要 |
The present invention stacks integrated circuits (ICs) into modules that conserve PWB or other board surface area. In another aspect, the invention provides a lower capacitance memory expansion addressing system and method and preferably with the CSP stacked modules provided herein. In a preferred embodiment in accordance with the invention, a form standard provides a physical form that allows many of the varying package sizes found in the broad family of CSP packages to be used to advantage while employing a standard connective flex circuitry design. In a preferred embodiment, the form standard will be devised of heat transference material such as copper to improve thermal performance. In an alternative embodiment, the form standard may include a heat spreader portion with mounting feet. In a preferred embodiment of the memory addressing system, a high speed switching system selects a data line associated with each level of a stacked module to reduce the loading effect upon data signals in memory access.
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申请公布号 |
US7524703(B2) |
申请公布日期 |
2009.04.28 |
申请号 |
US20050221597 |
申请日期 |
2005.09.07 |
申请人 |
ENTORIAN TECHNOLOGIES, LP |
发明人 |
CADY JAMES W.;WILDER JAMES;ROPER DAVID L.;WEHRLY, JR. JAMES DOUGLAS |
分类号 |
H01L21/00;H01L23/02;H01L23/31;H01L23/367;H01L23/498;H01L23/538;H01L25/10;H05K1/14;H05K1/18;H05K3/36 |
主分类号 |
H01L21/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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