| 摘要 |
A delay locked loop circuit is provided to improve the SI of clock by amending the duty of clock in the off mode. A delay locked loop circuit comprises an input buffer part(100), a delay locking part(200), and an output driver(300). The input buffer part comprises a buffer control unit(101), a clock buffer(110), the first clock driver(120), a duty correction block(130), and the second clock driver(150). The buffer control unit controls the on/OFF of the clock buffer according to the operation mode. The clock buffer outputs the internal clock by receiving the external clock(CLK) and the inversion external clock(CLKB). The first clock driver outputs the delay locking clock by using the internal clock and DLL enable signal as an input. The duty correction block amends the duty of the internal clock signal by assembling the internal clock signal and the DLL enable signal. The second clock driver outputs the direct clock(DIRCLK) by receiving the output signal of the duty correction block as an input. |
