| 发明名称 |
Timing loop based on analog to digital converter output and method of use |
| 摘要 |
A device and process to compensate for asymmetrical qualities of an analog input signal, if present, and generate a timing signal. The timing signal is then used for analog to digital conversion.
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| 申请公布号 |
US7525460(B1) |
申请公布日期 |
2009.04.28 |
| 申请号 |
US20070775757 |
申请日期 |
2007.07.10 |
| 申请人 |
MARVELL INTERNATIONAL LTD. |
发明人 |
LIU JINGFENG;OBERG MATS;KEIRN ZACHARY;NI BIN |
| 分类号 |
H03M1/10 |
主分类号 |
H03M1/10 |
| 代理机构 |
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代理人 |
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| 主权项 |
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