发明名称 I/O duty cycle and skew control
摘要 Circuits, methods and apparatus are provided to control the duty cycle of a signal. The rising and falling edges of a signal can be delayed independently to provide the selection or tuning of the duty cycle of the signal. Additionally, the delays can be used to reduce skew among both edges of signals being provided or transmitted by a data interface. The delays can be made to not cause a high-Z during a transition of the signal.
申请公布号 US7525360(B1) 申请公布日期 2009.04.28
申请号 US20070735401 申请日期 2007.04.13
申请人 ALTERA CORPORATION 发明人 WANG XIAOBAO;SUNG CHIAKANG;NGUYEN KHAI
分类号 H03K3/017 主分类号 H03K3/017
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