| 摘要 |
A memory device is fabricated with a graded composition tunnel insulator layer. This layer is formed over a substrate with a drain and a source region. The tunnel insulator is comprised of a graded SiC-GeC-SiC composition. A charge blocking layer is formed over the tunnel insulator. A trapping layer of nano-crystals is formed in the charge blocking layer. In one embodiment, the charge blocking layer is comprised of germanium carbide and the nano-crystals are germanium. The thickness and/or composition of the tunnel insulator determines the functionality of the memory cell such as the volatility level and speed. A gate is formed over the charge blocking layer.
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