发明名称 Fabrication method of wafer level chip scale packages
摘要 A method of fabricating wafer level chip scale packages may involve forming a hole to penetrate through a chip pad of an IC chip. A base metal layer may be formed on a first face of a wafer to cover inner surfaces of the hole. An electrode metal layer may fill the hole and rise over the chip pad. A second face of the wafer may be grinded such that the electrode metal layer in the hole may be exposed through the second face. By electroplating, a plated bump may be formed on the electrode metal layer exposed through the second face. The base metal layer may be selectively removed to isolate adjacent electrode metal layers. The wafer may be sawed along scribe lanes to separate individual packages from the wafer.
申请公布号 US7524763(B2) 申请公布日期 2009.04.28
申请号 US20050145994 申请日期 2005.06.07
申请人 SAMSUNG ELECTRONICS CO., LTD. 发明人 KIM SOON-BUM;KIM UNG-KWANG;MA KEUM-HEE;SONG YOUNG-HEE;SIM SUNG-MIN;OH SE-YONG;LEE KANG-WOOK;JEONG SE-YOUNG
分类号 H01L21/44;H01L23/28;C25D5/02;C25D7/12;H01L21/288;H01L21/48;H01L21/60;H01L21/768;H01L23/31;H01L23/48 主分类号 H01L21/44
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