| 摘要 |
A memory subsystem is disclosed. The memory subsystem includes a memory controller coupled to one or more memory modules. Each memory module comprises a buffer coupled to one or more memory ranks. A clock source is coupled to provide a clock signal to each of the memory modules. The memory controller is configured to convey a clock enable (CKE) command to one of the memory modules, the CKE command corresponding to a given memory rank. In response to the CKE command, a memory module buffer associated with the given memory rank is configured to convey a CKE disable signal to the given memory rank. The given memory rank is configured to disable operation of the clock signal within the given memory rank, responsive to the CKE disable signal.
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