| 摘要 |
Delay circuit parts are disposed between a signal converting part and buffers. Since the capacities of delay elements provided respectively for the wiring of output wiring parts are different, time lag is generated respectively in the output timings of digital output signals outputted from the signal converting part relative to control clock signals. The output timings of the digital output signals shift so that the simultaneous switching of the digital output signals is prevented. Accordingly, EMI noise can be reduced without requiring the use of a special interface standard or the addition of shield members.
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