发明名称 |
Memory module having a clock line and termination |
摘要 |
A memory module includes a signal line to carry a signal that traverses the signal line until reaching a termination at an end of the signal line. The module includes a clock line to carry a clock signal that traverses the clock line alongside the signal until the signal reaches a second termination at an end of the clock line. The module includes a first memory device connected to the signal line and the clock line such that the signal and the clock signal arrive at the first memory device at substantially the same time. The module includes a second memory device connected to the signal line and the clock line such that the signal and the clock signal arrive at the second memory device at substantially the same time and after the signal and the clock signal arrive at the first memory device. |
申请公布号 |
US7523247(B2) |
申请公布日期 |
2009.04.21 |
申请号 |
US20070683916 |
申请日期 |
2007.03.08 |
申请人 |
RAMBUS INC. |
发明人 |
LIAW HAW-JYH;NGUYEN DAVID |
分类号 |
G06F13/42;G06F13/00;G06F13/40;G11C5/00;G11C5/06;H05K1/02;H05K1/14;H05K7/14 |
主分类号 |
G06F13/42 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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