| 摘要 |
An electrostatic discharge protection structure is provided to reduce the area of electrostatic protection circuit by arranging the electrostatic protection circuit under the pad. An n-well(205) is formed in the place which is designed for an electrostatic protection circuit of a semiconductor substrate(200). A p well(210) is formed at the part of the n-well, and any element isolation film is not formed between the n-well and the p well. A first and a third p-type impurity regions(215a,215b,215c) are formed within the n-well, and a first and a third n-impurity areas(218a,218b,218c) are formed within the p well. A fourth n-impurity area(218d) is formed in the n-well, and a fourth p-type the impurity region(215d) is formed in the p well. A first bipolar transistor is formed between a third p-type impurity region, the n-well, and the p well. A second bipolar transistor is formed between the first n-impurity area, the p well and, the second n-impurity area. A third bipolar transistor is formed between the n-well, the p well, and the first n-impurity area. A fourth bipolar transistor is formed between the second p-type the impurity region, the n-well, and the third p-type impurity region. The fourth p-type the impurity region is electrically connected to a ground(VSS) and a voltage source line.
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