CHIP EQUALIZER AND EQUALIZING METHOD

摘要

A chip equalizer and an equalizing method for minimizing the computational complexity for the signal demodulation according to the performance of a receiver are provided to minimize the power consumption of the reception system. A delay control module(3210) recognizes a domain in which the major signal is included from the signal distribution of the signal received from a tuner. According to the delay difference between the adjacent major signal, the delay control module determines the noises compensation region. One or more first unit delay modules(3220, 3240) delays the signal of the domain in which the major signal is included among the signal received through tuner. The first unit delay module outputs the delayed signal to the tap coefficient estimation module(3250). One or more second unit delay module(3230) delays the signal of the domain in which the major signal is not included among the signals received through the tuner.