发明名称 |
High density memory array for low power application |
摘要 |
A memory device includes a first bit line in a first conducting layer and a second bit line parallel to the first bit line. The second bit line is in a second conducting layer. The memory device includes a MOS select transistor and a word line coupled to a gate of the MOS select transistor. The word line is at an angle with respect to the first bit line and the second bit line. The memory device includes a first resistive memory element coupled between a source of the MOS select transistor and the first bit line. The memory device includes a second resistive memory element coupled between a drain of the MOS select transistor and the second bit line.
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申请公布号 |
US7515455(B2) |
申请公布日期 |
2009.04.07 |
申请号 |
US20070650244 |
申请日期 |
2007.01.05 |
申请人 |
QIMONDA NORTH AMERICA CORP. |
发明人 |
NIRSHL THOMAS;HAPP THOMAS |
分类号 |
G11C11/00 |
主分类号 |
G11C11/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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