OSCILLATOR CAPABLE OF GENERATING STEADY CLOCK SIGNAL

摘要

An oscillator is provided to generate a clock signal stably by generating a complementary clock signal by the logic combination of two input signals which are transited complementarily. A reference voltage generator(110) generates the reference voltage. A first input signal generator(120) generates a first input signal transited to high-low or low-high in response to a second clock signal and a reference voltage. A second input signal generator(130) generates a second input signal transited complementarily to the first input signal in response to the reference voltage and the first clock signal. A logic combination circuit(140) logically combines the first and second input signal and generates the complementary first and second clock signal according to the logic combination result. An input signal transited to low-high among the first and second input signals is provided to the logic combination circuit before the input signal transited to high-low.